This invention relates to semiconductor processing and in particular processing involving heating of a semiconductor material.
In the copending application Ser. No. 195,688, filed Oct. 9, 1980 now U.S. Pat. No. 4,350,537, there is described a process and apparatus for annealing ion implantation damage in semiconductor bodies. The process involves annealing by pulse heating an ion damaged semiconductor body to a temperature range within which the sheet resistivity of the ion implanted body falls to a low value. The sheet resistivity of an arsenic ion, for example, implanted layer in a silicon body is not a linear function of the annealing temperature, but has a definite minimum value at a temperature between 450.degree. and 600.degree. C. The sheet resistivity shows a slow rise with increasing anneal temperature up to about 750.degree. C. and then falls again at 800.degree. to 900.degree. C., this latter temperature being an example of that employed in previously conventional annealing processes. The process disclosed in the copending application involves a rapid excursion to the annealing temperature, for example, heating the body to 500.degree. C. within 20 to 30 seconds and maintaining it at 500.degree. C. for 30 seconds (pulse heating), or alternatively heating the body rapidly to 700.degree. C. and immediately allowing it to cool (triangular pulse). The former pulse heating method was found to be sufficient to anneal ion implanted silicon wafers except those with partially damaged surface layers, whereas the latter method was found to be sufficient to regrow a damaged surface layer and activate the implanted arsenic. Those pulse heating methods provided effective annealing in a far shorter period and at lower temperatures than the then convention high temperature furnace techniques, thus also avoiding undesirable diffusion of the ion implanted or other dopants, if any. In a specific example a number of initially 30 ohm cm single crystal silicon wafers, were bombarded with arsenic ions at an energy of 150 KeV to produce a sub-surface doping level of 6.times.10.sup.15 cm.sup.-2. A set of these wafers was treated to a conventional furnace annealing process involving heating at 650.degree. C. for 30 minutes. The resultant sheet resistivity, indicative of the efficiency of the annealing process, was 39.3.+-.0.2 ohms per square. Another set of wafers was pulse heated to 600.degree. C. for 30 seconds and had a resultant sheet resistivity of 30.8.+-.0.2 ohms per square. The pulse heating employs temperatures in the region where the semiconductor sheet resistivity has a minimum value, that is the "low temperature" minimum.